1. Field of the Invention
The present invention relates to a deposition method for a compound semiconductor forming semiconductor devices, and particularly to a deposition method for a semiconductor with a heterostructure forming compound semiconductor devices including photo devices such as a semiconductor laser and photodiode and electronic devices such as a HEMT (high electron mobility transistor) and MESFET (metal-semiconductor FET).
2. Description of the Related Art
Electronic devices and photo devices using III-V group compound semiconductors have been actively developed. For fabrication for these devices, the heterostructure in which different semiconductors are assembled by crystal growth is inevitably mounted. For example, in a distributed feedback laser (DFB laser), on the diffraction grating formed on the surface of a semiconductor layer, the crystal of a semiconductor must be grown without destroying the shape of the diffraction grating.
In deposition of the semiconductor with a heterostructure, since the optimum deposition temperature is dependent on the kinds of the materials, the temperature is often required to be changed during deposition. Further, in the case that the deposition is performed without change in the temperature, in switching the source gases, the already deposited semiconductor layer is exposed under high temperatures.
In common, in a III-V group compound semiconductor layer, part of the components, mainly, the atom of a V group element is easily desorbed within a range of crystal growth temperature. Accordingly, when a semiconductor having another composition is deposited thereon without any contrivance, a part of crystal is thermally dissociated, which generates the irregularities on the crystal surface, deteriorates the morphology of the semiconductor layer, and lowers the steepness of the change in the composition at the hetero interface. For example, the diffraction grating constituting a DFB laser is destroyed due to the heat dissociation, and the heat deterioration of the crystal obstructs the improvement in the device characteristic.
Conventionally, in the process of heating a III-V group compound semiconductor, for preventing the heat deterioration of the semiconductor crystal, the source gas of the V group element such as As (arsenic) and P (phosphorus) exist in an ambience surrounding the deposited semiconductor in a sufficient amount.
In particular, when vapor deposition is performed by changing the deposition temperature or switching source gases, a V group element is supplied for preventing the heat deterioration of a crystal. The method is described, for example, in the following literature:
[1] H. Kamei and H. Hayashi, Journal of Crystal Growth 107, 1991, pp. 567-572, North-Holland.
Next, the processes of deposition of an InGaAs layer on an InP layer will be described with reference to FIG. 1, FIGS. 2A to FIG. 2D. FIG. 1 is a sequence of gas supply in crystal deposited; and FIGS. 2A to FIG. 2D shows the states of layers grown according to the sequence of FIG. 1.
First, as shown in FIG. 2A, TMIn (trimethylindium) and PH.sub.3 (phosphine) are supplied on an InP substrate 101, to deposit an InP layer 102. Next, as shown in FIG. 2B, the supply of TMIn is stopped, and the InP layer 102 is exposed in an ambience of PH.sub.3. After that, as shown in FIG. 2C, the supply of gas is switched from PH.sub.3 to AsH.sub.3 (arsine), to expose the InP layer 102 in an ambience of AsH.sub.3. Then, the mixed gas of ASH.sub.3, TMIn and TEGa (triethylgallium) is supplied on the surface of the InP layer 102. Thus, as shown in FIG. 2D, an InGaAs layer 103 is deposited on the InP layer 102.
In this method, for example, as shown in FIG. 2C, P (phosphorous) is desorbed from the surface of the InP layer 102, or it is substituted by As (arsenic). For preventing this phenomenon, it may be considered to short the supply time of AsH.sub.3.
However, even if the gas switching time is shortened, since P in the InP layer 102 reacts with As or AsH.sub.3 in the ambience, it is difficult to prevent the desorption of P from the InP layer 102 which is essentially generated, and to prevent the reaction with the P and As, which has a limitation to the control of steepness at the hetero interface.
Further, as a result of examining the photoluminescence (PL) by changing the supply time of AsH.sub.3 to the periphery of the InP layer, along with an increase in the supply time of AsH.sub.3, the peak of the PL intensity is shifted on the lower photon energy side and the line width of the PL is broadened. This is reported by the following literature. Therefore, it becomes apparent that the supply time of AsH.sub.3 for a long time cannot stabilize the surface of InP.
[2] J. Hergeth et al., Journal of Crystal Growth 107, 1991, pp. 537-542, North-Holland.
In addition, even in deposition of the InP layer on the InGaAs layer, the desorption of the As of the InGaAs layer and the reaction with As and P, PH.sub.3 cannot be avoided.